ADPCM codec: from system level description to versatile HDL model

Due to the rapid increase in the system complexity of modern telecommunication products, two main challenges exist for a system design flow meeting the arising demands: 1) provide a platform for fast algorithmic and architectural design exploration and optimization from system to gate level, which guarantees high quality of results (QoR) and enables full and seamless design verification; 2) provide a platform for design reuse. In this paper, we show how a design flow based on fast system simulation, behavioral synthesis and power analysis is used for the commercial implementation of an ADPCM (Adaptive Differential Pulse Code Modulation) codec module in record time, simultaneously meeting all design constraints and creating a versatile system and HDL model ready for design reuse