A formal method for specification and refinement of real-time systems

A new formal method for the specification, of real-time system requirements and their refinement to a design architecture is set out here. This integrated method is derived from a recently developed formal semantics, logic and refinement calculus for the IEEE standard hardware specification language VHDL. The specification format consists of three-phase “before, during and after” logical schemas, and comes with a combinatorial schema calculus and a refinement theory. The look and feel is reminiscent of Z and VDM and is intended to present an “upgrade path” to real-time for users with specification skills in these languages