A formal method for specification and refinement of real-time systems

Author

Breuer, Peter T. ; Madrid, Natividad Martinez ; Sanchez, L. ; Marin, Andres ; Kloos, Carlos Delgado

Author_Institution

Dept. de Ingenieria de Sistemas Telematicos, Univ. Politecnica de Madrid, Spain

fYear

1996

fDate

12-14 Jun 1996

Firstpage

200

Lastpage

204

Abstract

A new formal method for the specification, of real-time system requirements and their refinement to a design architecture is set out here. This integrated method is derived from a recently developed formal semantics, logic and refinement calculus for the IEEE standard hardware specification language VHDL. The specification format consists of three-phase “before, during and after” logical schemas, and comes with a combinatorial schema calculus and a refinement theory. The look and feel is reminiscent of Z and VDM and is intended to present an “upgrade path” to real-time for users with specification skills in these languages

Keywords

formal logic; formal specification; hardware description languages; real-time systems; refinement calculus; design architecture; formal method; formal semantics; hardware specification language; logic; logical schemas; real-time systems; refinement; refinement calculus; specification; specification format; Calculus; Hardware; Logic design; Real time systems; Solids; Specification languages; Standards development; Telecommunication standards;

fLanguage

English

Publisher

ieee

Conference_Titel

Real-Time Systems, 1996., Proceedings of the Eighth Euromicro Workshop on

Conference_Location

L´Aquila

ISSN

1068-3070

Print_ISBN

0-8186-7496-2

Type

conf

DOI

10.1109/EMWRTS.1996.557891

Filename

557891