Title :
The FLYSIG prototyping approach
Author :
Hardt, Wolfram ; Kleinjoahann, B. ; Rettbergr, A.
Author_Institution :
Dept. of Comput. Sci., Paderborn Univ., Germany
Abstract :
We present a customized approach to rapid prototyping based on a new chip design. The chip is named FLYSIG and adapts the prototyping architecture to the target architecture and the application domain in view. The chip architecture is scalable according to the requirements of arithmetic operators and interconnection flexibility. The prototyping chip is configurable in terms of operator functionality and operator interconnection. A FLYSIG prototyping chip with 720 add/sub operators has already been designed and a smaller version is just running through the fab. The design process of FLYSIG based rapid prototyping is supported by tools providing automated scheduling, performance analysis and code generation. The FLYSIG prototyping approach is illustrated by an example of reasonable complexity, i.e., a nested loop convolution algorithm which could be prototyped with the FLYSIG approach easily
Keywords :
digital signal processing chips; embedded systems; field programmable gate arrays; high level synthesis; performance evaluation; reconfigurable architectures; scheduling; DSP chip; FLYSIG prototyping approach; arithmetic operators; automated scheduling; chip design; code generation; configurable prototyping chip; customized approach; embedded systems; interconnection flexibility; nested loop convolution algorithm; operator functionality; operator interconnection; performance analysis; rapid prototyping; scalable chip architecture; Clocks; Computer architecture; Delay; Design methodology; Embedded system; Field programmable gate arrays; Laboratories; Prototypes; Signal design; Timing;
Conference_Titel :
Rapid System Prototyping, 2000. RSP 2000. Proceedings. 11th International Workshop on
Conference_Location :
Paris
Print_ISBN :
0-7695-0668-2
DOI :
10.1109/IWRSP.2000.855207
