A Verilog to C compiler

This paper describes a compiler which converts from Verilog to C. The output is then compiled to machine native code and tends to execute faster than native-mode Verilog simulation because the compiler preserves only the synthesis semantics, not the simulation semantics of Verilog, and also performs logic minimisation. Buses of up to 32 or 64 bits can be modelled as C integers, whereas larger buses are automatically split. We describe the motivation, method and quality of the results