Generic queue scheduling: concepts and VLSI

Quality of service and network controllability are issues that have yet to be clearly defined for broadband packet switching networks. One method of influencing the quality of service and the controllability of packet switched networks is queue scheduling. Unfortunately, defining an optimal queue scheduling method is highly dependent upon the cost function chosen for a particular switch implementation. Therefore, the authors propose a VLSI generic queue scheduler that can emulate a wide variety of queue scheduling methods. They implement the VLSI generic queue scheduler using a VLSI system synthesis tool, OASIS, and through measurements explore the size and speed of various system configurations. The process of employing some scheduling methods in this architecture is also detailed