DocumentCode
2213638
Title
An Interior Point Optimization Solver for Real Time Inter-frame Collision Detection: Exploring Resource-Accuracy-Platform Tradeoffs
Author
Leung, Brian ; Wu, Chih-Hung ; Memik, Seda Ogrenci ; Mehrotra, Sanjay
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
fYear
2010
fDate
Aug. 31 2010-Sept. 2 2010
Firstpage
113
Lastpage
118
Abstract
We present and compare implementations of an affine interior-point algorithm for real-time collision detection on a GPGPU and an FPGA. This particular interior-point algorithm is distinguished from other collision detection methods by its ability to perform detection between pairs of objects undergoing fast rotational and translational movement. This enables inter-frame collision detection, i.e. collision that might occur during the transition from one frame to another. In our design for the FPGA, we implemented the algorithm both in single-precision floating point and 32-bit fixed point and analyzed the trade-off between resource usage, data accuracy/precision, and system efficiency. Then, we compare them to a floating point implementation on a GPGPU using CUDA. With an object resolution of 45 vertices (45 vertices representing each polyhedral object), our FPGA implementation processes 1562 frames/sec for floating point and 1350 frames/second for fixed point and offers an 11× speedup over the GPGPU implementation. With object resolutions greater than 242 vertices, our GPGPU implementation outperforms our FPGA implementations.
Keywords
computer graphic equipment; coprocessors; field programmable gate arrays; fixed point arithmetic; floating point arithmetic; linear programming; logic design; parallel architectures; real-time systems; FPGA; GPGPU; affine interior-point algorithm; interior point optimization solver; object resolution; real time inter-frame collision detection; resource-accuracy-platform tradeoffs; single precision floating point; CUDA; Collision detection; FPGA; GPGPU; Linear Programming;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications (FPL), 2010 International Conference on
Conference_Location
Milano
ISSN
1946-1488
Print_ISBN
978-1-4244-7842-2
Type
conf
DOI
10.1109/FPL.2010.31
Filename
5694230
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