DocumentCode
2213650
Title
Reconfigurable instruction set processors: a survey
Author
Barat, Francisco ; Lauwereins, Rudy
Author_Institution
Katholieke Univ., Leuven, Belgium
fYear
2000
fDate
2000
Firstpage
168
Lastpage
173
Abstract
Reconfigurable instruction-set processors have the capability to adapt their instruction sets to the application being executed through a reconfiguration in their hardware. Through this adaptation, they are expected to achieve a great improvement in performance compared to fixed instruction-set processors. In this paper, we discuss the different hardware aspects that have to be considered during the design of such a reconfigurable processor. The topics discussed include the coupling of the processor and the reconfigurable logic, the configuration, instruction coding and scheduling, granularity, the hardware cache and reconfigurability. A classification of current reconfigurable processors is carried out according to the discussed topics
Keywords
cache storage; instruction sets; logic design; microprocessor chips; performance evaluation; processor scheduling; reconfigurable architectures; reviews; configuration; granularity; hardware cache; hardware reconfiguration; instruction coding; instruction set adaptation; performance; processor-logic coupling; reconfigurability; reconfigurable instruction set processors; reconfigurable logic; reconfigurable processor classification; scheduling; survey; Acceleration; Application specific processors; Field programmable gate arrays; Hardware; Instruction sets; Microprocessors; Process design; Read only memory; Reconfigurable logic; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Rapid System Prototyping, 2000. RSP 2000. Proceedings. 11th International Workshop on
Conference_Location
Paris
ISSN
1074-6005
Print_ISBN
0-7695-0668-2
Type
conf
DOI
10.1109/IWRSP.2000.855217
Filename
855217
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