Power-constrained block-test list scheduling

Author

Muresan, Vlad ; Xiaojun Wang ; Muresan, Vlad ; Vladutiu, Mircea

Author_Institution

Dublin City Univ., Ireland

fYear

2000

fDate

2000

Firstpage

182

Lastpage

187

Abstract

A list scheduling approach is proposed in this paper to overcome the problem of unequal-length block-test scheduling under power dissipation constraints. An extended tree growing technique is also used in combination with the list scheduling algorithm in order to improve the test concurrency, having assigned power dissipation limits. Moreover, the algorithm features a power dissipation balancing provision. Test scheduling examples are discussed, highlighting further research steps towards an efficient system-level test scheduling algorithm

Keywords

integrated circuit design; integrated circuit testing; list processing; logic design; power utilisation; processor scheduling; extended tree growing technique; power dissipation balancing provision; power dissipation constraints; power-constrained block-test list scheduling; system-level test scheduling algorithm; test concurrency; unequal-length block-test scheduling; Circuit testing; Clocks; Concurrent computing; Logic testing; Performance evaluation; Polynomials; Power dissipation; Scheduling algorithm; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Rapid System Prototyping, 2000. RSP 2000. Proceedings. 11th International Workshop on

Conference_Location

Paris

ISSN

1074-6005

Print_ISBN

0-7695-0668-2

Type

conf

DOI

10.1109/IWRSP.2000.855220

Filename

855220