Title :
A 1860 kG CMOS gate array with GTL input flip-flop circuits
Author :
Tomobe, Katsuichi ; Takahashi, Toshiro ; Kawashima, Masatoshi ; Sonobe, Yasuo ; Kiyuna, Tadashi ; Yamamoto, Sigeru
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
A 1860 kG CMOS gate array with a high speed I/O circuit using 0.35 μm CMOS process technology, has been developed. 300 MHz synchronous data transmission through a 30 cm line has been achieved with a flip-flop circuit which can directly receive and store a low voltage swing signal. This circuit technique reduces the latency time of data transmission between 2 LSIs by as much as 1.7 ns compared with conventional circuits
Keywords :
CMOS logic circuits; flip-flops; large scale integration; logic arrays; 0.35 micron; 30 cm; CMOS gate array; GTL input flip-flop circuits; LSI; data transmission; high speed I/O circuit; latency time reduction; low voltage swing signal; CMOS process; CMOS technology; Circuits; Clocks; Data communication; Delay effects; Flip-flops; Frequency; Large scale integration; Low voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-3117-6
DOI :
10.1109/CICC.1996.510512
