DocumentCode
2213745
Title
Advanced 3D chip stack process for thin dies with fine pitch bumps using pre-applied inter chip fill
Author
Horibe, Akihiro ; Yamada, Fumiaki
Author_Institution
Assoc. of Super-Adv. Electron. Technol. (ASET), Yamato, Japan
fYear
2009
fDate
28-30 Sept. 2009
Firstpage
1
Lastpage
4
Abstract
A novel stack joining process using newly designed pre-applied underfill for specifically 3D stacked chip was developed. The 3D chip stack process using this technique enables process time reduction and improvement of 3D device reliability because the multi stacked chip experiences only one soldering temperature cycle for joining.
Keywords
fine-pitch technology; integrated circuit design; integrated circuit interconnections; integrated circuit reliability; soldering; stacking; 3D device reliability; advanced 3D chip stack process; fine pitch bumps; fine pitch interconnection; preapplied inter chip fill; soldering temperature cycle; thin dies; through silicon vias; Bandwidth; Cleaning; Joining processes; Packaging; Process design; Resins; Silicon; Stacking; Temperature; Through-silicon vias; 3D chip stack; Inter Chip Fill; Stack Joining process; fine pitch interconnection; thin chip; through silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
978-1-4244-4511-0
Electronic_ISBN
978-1-4244-4512-7
Type
conf
DOI
10.1109/3DIC.2009.5306555
Filename
5306555
Link To Document