Title :
Floating point datapaths with on-line built-in self speed test
Author :
Hagihara, Yasuhiko ; Inui, Shigeto ; Okamoto, Fuyuki ; Nishida, Masato ; Nakamura, Toshihiko ; Yamada, Hachiro
Author_Institution :
Microelectron. Res. Labs., NEC Corp., Tokyo, Japan
Abstract :
This paper describes floating point (FP) datapaths developed for graphics and simulation applications. The datapaths are fabricated using 0.35 μm CMOS technology and embedded in a 125 MHz, 290 MFLOPS vector pipelined processor for use in supercomputers. A new on-line test technique has been developed for the purpose of improving reliability under actual operating conditions. The technique makes it easy to detect not only static faults but also delay faults, which have traditionally been difficult to detect
Keywords :
CMOS logic circuits; adders; built-in self test; computer testing; dividing circuits; fault location; floating point arithmetic; integrated circuit testing; logic testing; microprocessor chips; multiplying circuits; pipeline arithmetic; vector processor systems; 0.35 micron; 125 MHz; 290 MFLOPS; CMOS technology; built-in self speed test; delay faults; fault detection; floating point datapaths; graphics applications; online BIST; reliability; simulation applications; static faults; supercomputer use; vector pipelined processor; Automatic testing; CMOS process; CMOS technology; Clocks; Delay; Fault detection; Graphics; National electric code; Pipelines; Supercomputers;
Conference_Titel :
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-3117-6
DOI :
10.1109/CICC.1996.510513
