Evaluation of Fault-Mitigation Schemes for Fault-Tolerant Dynamic MPSoC

One trend dealing with the growing computational power needs is to implement multi-processor system-on-a-chip (MPSoC) using Commercial Off-The-Shelf (COTS) partially reconfigurable architectures. However the low Non-Recurring Engineering (NRE) cost solution provided by commercial FPGAs must take into account the high sensitivity to electronic defects. Fault-tolerance schemes, which prevent their architectures from being defective during products life-time, can decrease the system computing power. Therefore, building such fault-tolerant system needs an analytical model to analyze the effect of fault mitigation schemes on the system performance. This paper presents an analytical approach for a fault-tolerant dynamic multi-processor system-on-a-chip (FT-DyMPSoC) which is able to resist to predominant fault in FPGAs - Single Event Upset. The analytical model is introduced to assess the performance, the reliability and the trade-off of a fault-tolerant MPSoC system. Several comparisons with classical fault-tolerance solutions to enhance our solution advantages are also given.