A routerless system level interconnection network for 3D integrated systems

This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of next generation multicore systems and can efficiently support multiple programming models including symmetric common memory architectures. We present preliminary data from simulations of a network model and the design of a demonstration chip in stacked 3D integration technology. Our simulations demonstrate that our fully distributed routing and control system allocates system bandwidth fairly with minimal overhead, even when demand is close to network saturation.