DocumentCode
2213817
Title
Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine
Author
Wray, Stephen ; Luk, Wayne ; Pietzuch, Peter
Author_Institution
Dept. of Comput., Imperial Coll. London, London, UK
fYear
2010
fDate
Aug. 31 2010-Sept. 2 2010
Firstpage
163
Lastpage
166
Abstract
In this paper we present an analysis of using run-time reconfiguration of reconfigurable hardware to modify trading algorithms during use. This provides flexibility in algorithm design, enabling the implementation to be reactive to changes in market conditions, increasing in performance. We study what can be achieved to reduce performance loss in algorithms while reconfiguration takes place, such as buffering information during this time. Our results show our average partial reconfiguration time is 0.002091 seconds, using historic highest market data rates would result in about 5,000 messages being missed or require buffering. This is the worst case scenario, normally the system would only require a fraction of messages. The reconfiguration time is acceptable if it is under the required limit by the user to prevent business performance suffering.
Keywords
algorithm theory; field programmable gate arrays; reconfigurable architectures; stock markets; algorithmic trading engine; buffering information; market data; reconfigurable hardware; run time reconfiguration; Algorithm Trading; Run-Time Reconfiguration;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications (FPL), 2010 International Conference on
Conference_Location
Milano
ISSN
1946-1488
Print_ISBN
978-1-4244-7842-2
Type
conf
DOI
10.1109/FPL.2010.39
Filename
5694239
Link To Document