Title :
Delay analysis and design exploration for 3D SRAM
Author :
Chen, Xi ; Davis, W. Rhett
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Abstract :
The emerging three-dimension (3D) integration technology provides a solution to reduce delay in SRAM. In this paper, we present a physical based delay analysis approach to explore 3D SRAM design options. Our analysis can be used to optimize the 3D SRAM timing performance at both sub-array and system level. Design examples based on the MITLL 3D process are constructed to demonstrate the trade-offs. As the analysis results show, the optimized 3D sub-array provides up to 20% extra improvement for SRAM access time reduction.
Keywords :
SRAM chips; delays; logic design; 3D SRAM design; MITLL 3D process; SRAM access time reduction; delay analysis approach; design exploration; system level; three-dimension integration technology; Delay; Design optimization; Equations; Integrated circuit interconnections; Performance analysis; Random access memory; Through-silicon vias; Timing; Very large scale integration; Wire;
Conference_Titel :
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-4511-0
Electronic_ISBN :
978-1-4244-4512-7
DOI :
10.1109/3DIC.2009.5306558
