Title :
Implementation of VLSI-oriented FELICS algorithm using Pseudo Dual-Port RAM
Author :
Rejusha, M. ; Jayanthi, K.B.
Author_Institution :
Dept. of Electron. & Commun. Eng., K.S. Rangasamy Coll. of Technol., Tiruchengode, India
Abstract :
This paper presents a fast, efficient, lossless image compression algorithm named FELICS. This consists of two techniques named simplified adjusted binary code and GOLOMB-Rice code which provide lossless compression for high throughput applications. Two-level parallelism with four-stage pipelining is adopted. Pseudo Dual-Port RAM is used which improves the processing speed and decreases area and power consumption. The proposed architecture can be used for high definition display applications.
Keywords :
binary codes; data compression; image coding; parallel processing; pipeline processing; random-access storage; GOLOMB-rice code; VLSI-oriented FELICS algorithm; fast efficient lossless image compression algorithm; four-stage pipelining; high definition display application; power consumption; processing speed; pseudo dual-port RAM; simplified adjusted binary code; two-level parallelism; Algorithm design and analysis; Binary codes; Encoding; Hardware; Image coding; Random access memory; Throughput; Full high-definition (HD); Parallelism and Pseudo Dual-Port RAM (PDPRAM);
Conference_Titel :
Pattern Recognition, Informatics and Medical Engineering (PRIME), 2012 International Conference on
Conference_Location :
Salem, Tamilnadu
Print_ISBN :
978-1-4673-1037-6
DOI :
10.1109/ICPRIME.2012.6208289
