Title :
Power management technique for 1-V LSIs using embedded processor
Author :
Shigematsu, Satoshi ; Mutoh, Shin´ichiro ; Matsuya, Yasuyuki
Author_Institution :
NTT LSI Labs., Atsugi, Japan
Abstract :
A new power management technique is proposed for low-power, high-speed LSIs. This technique reduces the power consumption and enhances the performance of an LSI by using an embedded small processor to control the sleep modes and the processing of the LSI. Using this technique for a low-power DSP, the total power is reduced to about 10% of one without this technique, while maintaining the speed performance in 1-V LSIs
Keywords :
digital signal processing chips; integrated circuit design; large scale integration; leakage currents; 1 V; embedded small processor; high-speed LSIs; low-power DSP; power consumption; power management technique; sleep modes; speed performance; Circuits; Digital signal processing; Energy management; Large scale integration; Leakage current; Logic; Low voltage; MOSFETs; Portable media players; Process control;
Conference_Titel :
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-3117-6
DOI :
10.1109/CICC.1996.510523
