Implementing and evaluating adiabatic arithmetic units

In recent years, several adiabatic logic architectures have been proposed for low-power VLSI design. However, no work has been presented describing the implementation and evaluation of nontrivial adiabatic circuits. We have evaluated a specific adiabatic architecture and used it in the design of low-power arithmetic units. We investigated implementation issues specific to adiabatic system development and performed a systematic comparison of our designs with corresponding CMOS circuits. In this paper we describe our adiabatic designs, discuss implementation issues at the logic and architectural level, and report our empirical findings