Title :
Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration
Author :
Bea, J.C. ; Murugesan, M. ; Ohara, Y. ; Noriki, A. ; Kino, H. ; Lee, K.-W. ; Fukushima, T. ; Tanaka, T. ; Koyanagi, M.
Author_Institution :
Grad. Sch. of Eng., Dept. of Bioeng. & Robot., Tohoku Univ., Sendai, Japan
Abstract :
Mechanical stress, crystal defects, and metal contamination in thinned silicon substrates with and without intrinsic gettering (IG) zone have been investigated for three-dimensional (3D) integration. The remnant stress existing after wafer thinning was evaluated using angle-(5deg) polished silicon wafers by micro-Raman spectroscopy (muRS). The metal contamination in the thinned silicon substrates has been evaluated by a capacitance-time (C-t) measurement method using MOS capacitors in which the thinned silicon substrates were diffused with metallic impurities such as Cu and Au used for through-silicon via (TSV) and metal microbump in 3D LSI.
Keywords :
MOS capacitors; Raman spectroscopy; capacitance measurement; integrated circuit design; integrated circuit interconnections; integrated circuit reliability; large scale integration; time measurement; 3D LSI; 3D integration; MOS capacitors; Si; capacitance-time measurement method; crystal defects; intrinsic gettering zone; mechanical stress; metal microbump; metallic impurities; microRaman spectroscopy analysis; polished silicon wafer; remnant stress; thinned silicon substrates; three-dimensional integration; through-silicon via; wafer thinning; Capacitance measurement; Contamination; Gettering; Impurities; MOS capacitors; Pollution measurement; Silicon; Spectroscopy; Stress; Time measurement;
Conference_Titel :
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-4511-0
Electronic_ISBN :
978-1-4244-4512-7
DOI :
10.1109/3DIC.2009.5306568
