Title :
3D interconnects for dense die stack packages
Author :
Mirkarimi, L. ; Huynh, M. ; Savalia, P. ; Oganesian, V.
Author_Institution :
Tessera, San Jose, CA, USA
Abstract :
A unique 3D interconnect fabricated using a wafer level stack package technology is presented. The prototype module, a package in package is described and the environmental stress testing results are discussed.
Keywords :
electronics packaging; integrated circuit interconnections; 3D interconnect; dense die stack package; environmental stress testing; wafer level stack package technology; Packaging machines; Prototypes; Resists; Silicon; Stacking; Testing; Through-silicon vias; Wafer bonding; Wafer scale integration; Wire;
Conference_Titel :
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-4511-0
Electronic_ISBN :
978-1-4244-4512-7
DOI :
10.1109/3DIC.2009.5306574
