Title :
An efficient video decoder design for MPEG-2 MP@ML
Author :
Li, Jui-Hua ; Ling, Nam
Author_Institution :
Dept. of Comput. Eng., Santa Clara Univ., CA, USA
Abstract :
In this paper, we present an efficient MPEG-2 video decoder architecture design to meet MP@ML real-time decoding requirement. The overall architecture, as well as the design of the major function-specific processing blocks, such as the variable-length decoder, the inverse 2-D discrete cosine transform unit, and the motion compensation unit, are discussed. A hierarchical and distributed controller approach is used and a bus-monitoring model for different bus arbitration schemes to control external DRAM accesses is developed and the system is simulated. Practical issues and buffer sizes are addressed. With a 27 MHz clock, our architecture uses much fewer than the 667 cycles, upper bond for the MP@ML decoding requirement, to decode each macroblock with a single external bus and DRAM
Keywords :
DRAM chips; decoding; motion compensation; video coding; DRAM accesses; MPEG-2 MP@ML; buffer sizes; bus arbitration schemes; bus-monitoring model; function-specific processing blocks; inverse 2-D discrete cosine transform; motion compensation unit; variable-length decoder; video decoder architecture; video decoder design; Clocks; Computer architecture; Costs; Decoding; Discrete cosine transforms; Motion compensation; Random access memory; Solid modeling; Transform coding; Video coding;
Conference_Titel :
Application-Specific Systems, Architectures and Processors, 1997. Proceedings., IEEE International Conference on
Conference_Location :
Zurich
Print_ISBN :
0-8186-7959-X
DOI :
10.1109/ASAP.1997.606856