DocumentCode :
2214312
Title :
A methodology to characterize USB3 IO link signal margin variation in high volume manufacturing
Author :
Ji, Steven Yun ; Puligundla, Sudeep ; Qi, Xiaoning ; Ling, Michael
Author_Institution :
Intel Corporation, Santa Clara, California, USA
fYear :
2015
fDate :
16-22 Aug. 2015
Firstpage :
1329
Lastpage :
1334
Abstract :
High-speed IO performance verification is challenging due to system variations across high volume manufacturing. This paper presents a methodology to quantify variations caused by several IO subcomponents including transmitter, receiver, channel, test repeatability and concurrency effects. A tablet USB3 design was used as an example to illustrate the method.
Keywords :
Concurrent computing; Integrated circuit modeling; Performance evaluation; System-on-chip; Testing; Universal Serial Bus; IO performance; USB3; high-volume manufacturing; signal integrity; system margin;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electromagnetic Compatibility (EMC), 2015 IEEE International Symposium on
Conference_Location :
Dresden, Germany
Print_ISBN :
978-1-4799-6615-8
Type :
conf
DOI :
10.1109/ISEMC.2015.7256364
Filename :
7256364
Link To Document :
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