Evaluation of energy-recovering interconnects for low-power 3D stacked ICs

Author

Asimakopoulos, P. ; Van der Plas, G. ; Yakovlev, A. ; Marchal, P.

Author_Institution

Sch. of EECE, Newcastle Univ., Newcastle upon Tyne, UK

fYear

2009

fDate

28-30 Sept. 2009

Firstpage

1

Lastpage

5

Abstract

Energy-recovering schemes have been proposed in the literature as an alternative approach to low-power design, while their performance has been demonstrated to be extremely promising when driving large capacitive loads, such as clock distribution networks. This work investigates the potential of the energy-recovering methodology for improving the energy efficiency of through-silicon via (TSV) interconnects in 3D ICs.

Keywords

clocks; distribution networks; integrated circuit design; integrated circuit interconnections; low-power electronics; monolithic integrated circuits; capacitive loads; clock distribution network; energy efficiency; energy-recovering interconnects; low-power 3D stacked IC; low-power design; through-silicon via interconnects; CMOS logic circuits; Clocks; Driver circuits; Drives; Energy dissipation; Energy efficiency; Frequency; Integrated circuit interconnections; Parasitic capacitance; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

3D System Integration, 2009. 3DIC 2009. IEEE International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4244-4511-0

Electronic_ISBN

978-1-4244-4512-7

Type

conf

DOI

10.1109/3DIC.2009.5306581

Filename

5306581