DocumentCode :
2214579
Title :
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)
Author :
Ye, Yaoyao ; Duan, Lian ; Xu, Jiang ; Ouyang, Jin ; Hung, Mo Kwai ; Xie, Yuan
Author_Institution :
Electron. & Comput. Eng. Dept., Hong Kong Univ. of Sci. & Technol., Hong Kong, China
fYear :
2009
fDate :
28-30 Sept. 2009
Firstpage :
1
Lastpage :
6
Abstract :
Networks-on-chip (NoC) is emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoC). In traditional electronic NoCs, high bandwidth can be obtained by increasing the number of parallel metallic wires at the cost of more energy consumption. Optical NoCs are thus proposed to achieve low-power ultra-high-bandwidth data transmission in optical domain. Electronic control technology could be a complement to the optical networks. Besides NoCs, three-dimensional integrated circuits (3D ICs) are another attractive solution for system performance improvement by reducing the interconnect length. The investigation of using 3D IC as a platform for the realization of mixed-technology electronic-controlled optical NoC has not been addressed until recently. In this paper, we propose a 3D electronic-controlled optical NoC implemented in a TSV-based (through-silicon via) two-layer 3D chip. The upper device layer is an optical layer. It integrates an optical data transmission network, which is responsible for optical payload packets transmission. The bottom device layer is an electronic layer. It contains an electronic control network, which is used to route control packets and configure the optical network. We built an 8 times 8 mesh-based 3D optical NoC, with a 45 nm electronic control network. Power comparison with a matched 2D electronic NoC shows that the optical NoC can reduce power consumption significantly. For 2048 B packets, it has a 70% power reduction. End-to-end delay (ETE delay) and network throughput of the two NoCs under varying injection rates were evaluated for comparison. The results show that ETE delay of the optical NoC is much smaller than the electronic NoC when the network becomes congested. Take 4096 B packets for example, it is 18.7 mus in the optical NoC with an injection rate of 0.5, while 33.5 mus in the electronic one. A maximum throughput of 478 Gbps can be offered by the optical NoC using 32 Gbps optical link bandwi- dth. Because of the low resource utilization of circuit switching, the maximum throughput of the optical NoC is slightly lower than the electronic one.
Keywords :
integrated optoelectronics; network-on-chip; optical interconnections; 3D IC; 3D optical networks-on-chip; MPSoC; bit rate 32 Gbit/s; bit rate 478 Gbit/s; bottom device layer; circuit switching; electronic control technology; electronic layer; end-to-end delay; energy consumption; interconnect length; key on-chip communication architecture; low-power ultra-high-bandwidth data transmission; mixed-technology electronic-controlled optical NoC; multiprocessor systems-on-chip; network throughput; optical data transmission network; optical layer; optical link bandwidth; optical payload packets transmission; parallel metallic wires; power consumption; three-dimensional integrated circuits; through-silicon via; time 18.7 mus; time 33.5 min; two-layer 3D chip; Data communication; Energy consumption; Integrated optics; Multiprocessing systems; Network-on-a-chip; Optical control; Optical fiber networks; Optical interconnections; Three-dimensional integrated circuits; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-4511-0
Electronic_ISBN :
978-1-4244-4512-7
Type :
conf
DOI :
10.1109/3DIC.2009.5306588
Filename :
5306588
Link To Document :
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