IC-package co-design and analysis for 3D-IC designs

The implementation of a 3D IC is typically accomplished by multiple design teams, in multiple geographies, using a variety of design tools. Types of designs include a simple package, with an analog die and a digital die placed side-by-side and more complex designs include die stacks of multiple analog or digital dies in face-to-face configurations connecting with micro bumps. Through-silicon-vias (TSV´s) provide an extra level of complexity allowing an individual die to connect to the component below and above it in the stack. Interposers (silicon or organic) provide greater functional density, performance, and reduced cost. Also used in 3D-IC design are package-in-package, and package-on-package design styles. This paper discusses five key ingredients necessary for the successful design of a 3D-IC regardless which method above is used. These five items are (i) logical system-level integration to connect the system of ICs and packages, including support of layout-vs-schematic (LVS) checks (ii) physical co-design across IC and package boundaries through the sharing of component abstracts and cross-fabric functionality (iii) timing, power, and thermal-based design of the 3D-IC system in context of the package (iv) package-aware system simulation of 3D-IC circuitry (v) management of physical and logical engineering change orders (ECO´s).