Two dimensional quantitative study of the performance of low temperature epitaxial silicon emitter bipolar transistors with side-wall spacer

Detailed two dimensional simulations were carried out on side-wall spacer self-aligned (1) polysilicon emitter bipolar transistor and (2) low-temperature epitaxial emitter bipolar transistor. It is shown that the lateral extrinsic-base-to-intrinsic-base encroachment is improved in the epitaxial emitter transistor resulting in reduced peripheral punchthrough currents. Also, the maximum surface electric field is strongly reduced in the epitaxial emitter structure resulting in smaller tunneling currents. Finally, the calculated transient delays is shorter for the epitaxial transistor than for the polysilicon emitter transistor