DocumentCode
2214683
Title
High performance twin silicon nanowire MOSFET(TSNWFET) on bulk si wafer
Author
Suk, Sung Dae ; Yeo, Kyoung Hwan ; Cho, Keun Hwi ; Li, Ming ; Yeoh, Yun Young ; Lee, Sung-Young ; Kim, Sung Min ; Yoon, Eun Jung ; Kim, Min Sang ; Oh, Chang Woo ; Kim, Sung Hwan ; Kim, Dong-Won ; Park, Donggun
Author_Institution
R&D Center, Samsung Electron. Co., Yongin
Volume
1
fYear
2006
fDate
22-25 Oct. 2006
Firstpage
212
Lastpage
213
Abstract
Gate-all-around twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on bulk Si wafer is successfully fabricated to achieve extremely high drive currents of 2.37 mA/mum for n-channel and 1.30 mA/mum for p-channel TSNWFETs with mid-gap TiN metal gate. It also shows good short channel effects immunity down to 30 nm gate length due to GAA structure and nanowire channel. The effect of bottom parasitic transistor in TSNWFET is also investigated.
Keywords
MOSFET; monolithic integrated circuits; nanowires; bulk Silicon wafer; metal-oxide-semiconductor; nanowire channel; parasitic transistor; radius 5 nm; size 30 nm; twin silicon nanowire MOSFET; Annealing; Etching; Hydrogen; MOSFET circuits; Nanoscale devices; Silicon compounds; Silicon germanium; Threshold voltage; Tin; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. IEEE
Conference_Location
Gyeongju
Print_ISBN
978-1-4244-0540-4
Electronic_ISBN
978-1-4244-0541-1
Type
conf
DOI
10.1109/NMDC.2006.4388844
Filename
4388844
Link To Document