Title :
A 35 Gbit/s throughput 64 kbit CMOS buffer SRAM
Author :
Alowersson, Jonas ; Andersson, Per
Author_Institution :
Dept. of Comput. Eng., Lund Univ., Sweden
Abstract :
A 64 kbit 0.8-μm pure CMOS buffer memory with 256 bit word-length and 3.6 ns cycle time, allowing 35 Gbit/s throughput, is presented. The memory consumes 1.5 W at the maximum frequency. The short cycle time is achieved through the use of a synchronously pipelined address decoder with one internal level of latches. The address decoder, based on TSPC latches, is described in detail
Keywords :
CMOS memory circuits; SRAM chips; buffer storage; 0.8 micron; 1.5 W; 256 bit; 3.6 ns; 35 Gbit/s; 64 kbit; CMOS buffer SRAM; TSPC latches; buffer memory; cycle time; synchronously pipelined address decoder; Circuits; Clocks; Decoding; Delay; Energy consumption; Latches; Random access memory; Read-write memory; Throughput; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-3117-6
DOI :
10.1109/CICC.1996.510555
