A 336-kbit content addressable memory for highly parallel image processing

Author

Ogura, Takeshi ; Nakanishi, Mamoru ; Baba, Tatsuo ; Nakabayashi, Yasuji ; Kasai, Ryota

Author_Institution

NTT LSI Labs., Atsugi, Japan

fYear

1996

fDate

5-8 May 1996

Firstpage

273

Lastpage

276

Abstract

This paper describes a 336-kbit (4 kwords×84 bits) Content Addressable Memory (CAM) LSI with dedicated functions for highly parallel image processing. This LSI can operate as a SIMD PE array, and is a key component of a CAM-based system, HiPIC (Highly-parallel Integrated Circuits and System). New hit-flag generation and multiple-response-resolution schemes are also incorporated in this LSI. A total of 4.2 million transistors are integrated using 0.5 μm CMOS process technology. The CAM LSI and HiPIC concept described here will make a significant contribution to the development of real-time image processing systems

Keywords

CMOS memory circuits; VLSI; content-addressable storage; image processing; image processing equipment; parallel processing; real-time systems; 0.5 micron; 336 kbit; CAM LSI; CMOS process technology; HiPIC; SIMD PE array; content addressable memory; dedicated functions; highly parallel image processing; hit-flag generation scheme; multiple-response-resolution scheme; real-time image processing systems; Associative memory; CADCAM; CMOS process; Computer aided manufacturing; Data processing; Image processing; Integrated circuit technology; Large scale integration; Parallel processing; Reconfigurable logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Conference_Location

San Diego, CA

Print_ISBN

0-7803-3117-6

Type

conf

DOI

10.1109/CICC.1996.510557

Filename

510557