Title :
3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)
Author :
Van Olmen, J. ; Coenen, J. ; Dehaene, W. ; De Meyer, K. ; Huyghebaert, C. ; Jourdain, A. ; Katti, Guruprasad ; Mercha, A. ; Rakowski, M. ; Stucchi, M. ; Travaly, Y. ; Beyne, E. ; Swinnen, B.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
In this paper we demonstrate functional 3D circuits obtained by a 3D Stacked IC approach using Die-to-Wafer Hybrid Collective bonding with Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 130 nm CMOS process on 200 mm wafers. The top die is thinned down to 25 mum and bonded to the landing wafer by a combination of polymer bonding and copper to copper thermocompression bonding. Top and landing wafers contain CMOS finished with 2 levels of metal in Copper/Oxide. Ring oscillators consisting of inverters distributed over both top and bottom dies interconnected through up to 40 TSVs are used to demonstrate the process. This paper focuses on integration issues solved during process development and electrical characterization of the obtained TSVs.
Keywords :
CMOS integrated circuits; wafer bonding; 3D stacked IC demonstrator; CMOS; Cu; complementary metal-oxide-semiconductor; copper through silicon vias; functional 3D circuit; hybrid collective die-to-wafer bonding; integrated circuit; inverter; polymer bonding; ring oscillator; size 130 nm; size 200 mm; size 25 mum; thermocompression bonding; CMOS process; Copper; Hybrid integrated circuits; Integrated circuit interconnections; Inverters; Polymers; Ring oscillators; Silicon; Through-silicon vias; Wafer bonding;
Conference_Titel :
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-4511-0
Electronic_ISBN :
978-1-4244-4512-7
DOI :
10.1109/3DIC.2009.5306600
