Title :
A rank-one update method for efficient processing of interconnect parasitics in timing analysis
Author :
Levy, H. ; Scott, W. ; MacMillen, D. ; White, Jacob
Author_Institution :
Synopsys
Keywords :
Delay; Driver circuits; Integrated circuit interconnections; Iterative algorithms; Parasitic capacitance; Permission; Reduced order systems; Resistors; Timing; Very high speed integrated circuits;
Conference_Titel :
Design Automation Conference, 2000. Proceedings 2000
Print_ISBN :
1-58113-187-9
DOI :
10.1109/DAC.2000.855280
