Title :
Scratchpad memory-global power optimization
Author :
Karthika, M. ; Rajasekaran, C.
Author_Institution :
Dept. of ECE, K.S. Rangasamy Coll. of Technol., Namakkal, India
Abstract :
Scratchpad Memories are widely employed in embedded systems as an alternative to caches because they achieve comparable performance with higher power efficiency. Here, Optimal SPM Mapping and Memory Power-Down techniques are used for minimize the total energy of the SPM. SPM mapping simply targets the minimum number of accesses to the main memory, i.e., active power. A global optimization should explicitly take into account memory access energy, leakage energy, and power-down/up energy penalty, to define the Optimal SPM mapping and Optimal memory power-down scheduling for minimizing the total energy in the memory sub-system. Synthesis results based on 1.32V CMOS standard-cell library shows that the proposed SPM reduces the power consumption by 25-30%.
Keywords :
digital storage; embedded systems; optimisation; power aware computing; CMOS standard-cell library; embedded systems; global optimization; leakage energy; memory access energy; memory power-down techniques; memory subsystem; optimal SPM mapping; optimal memory power-down scheduling; power efficiency; power-down/up energy penalty; scratchpad memories; scratchpad memory-global power optimization; Arrays; Embedded systems; Memory management; Program processors; Random access memory; Resource management; Hard Multiples; High Level Design; Higher radix; Modified Booth encoder;
Conference_Titel :
Pattern Recognition, Informatics and Medical Engineering (PRIME), 2012 International Conference on
Conference_Location :
Salem, Tamilnadu
Print_ISBN :
978-1-4673-1037-6
DOI :
10.1109/ICPRIME.2012.6208343