Title :
A high throughput sort free VLSI architecture for wireless applications
Author :
Soundharya, S. ; Prakash, Gl
Author_Institution :
Dept. of Electron. & Commun., K.S. Rangasamy Coll. Of Technol., Tiruchengode, India
Abstract :
For high data rate Multiple Input Multiple Output technology is used in wireless communications. The use of multiple antennas at both transmitter and receiver (MIMO) significantly increases the capacity and spectral efficiency of wireless systems. This paper presents a Field Programmable Gate Array (FPGA) implementation for a 4 × 4 breadth first K-best MIMO decoder using a 64 Quadrature Amplitude Modulation (QAM) scheme. A novel sort free approach to path extension, as well as, quantized metrics result in a high throughput, low power and area. Finally, VLSI architectural tradeoffs are explored for a synthesized using synopsys the power analysis, throughput analysis in 120 nm technology. The power needed is 20.0025 μW.
Keywords :
MIMO communication; VLSI; antenna arrays; decoding; field programmable gate arrays; integrated circuit reliability; quadrature amplitude modulation; radio receivers; radio transmitters; 4×4 breadth first K-best MIMO decoder; 64 quadrature amplitude modulation scheme; FPGA; QAM scheme; field programmable gate array implementation; high data rate multiple input multiple output technology; high throughput sort free VLSI architecture; multiple antennas; path extension; power 20.0025 muW; power analysis; quantized metrics; receiver; size 120 nm; sort free approach; spectral efficiency; synopsys; transmitter; wireless communications; wireless systems; Computer architecture; Decoding; Detectors; MIMO; Measurement; Throughput; Very large scale integration; FPGA Kit; Multiple Input Multiple Output (MIMO); Sphere decoder; VLSI; Wireless;
Conference_Titel :
Pattern Recognition, Informatics and Medical Engineering (PRIME), 2012 International Conference on
Conference_Location :
Salem, Tamilnadu
Print_ISBN :
978-1-4673-1037-6
DOI :
10.1109/ICPRIME.2012.6208345
