Title :
Formal verification of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction
Author :
Velev, Miroslav N. ; Bryant, Randal E.
Author_Institution :
Carnegie Mellon University
Keywords :
Computer aided instruction; Computer science; Delay; Design automation; Formal verification; Logic; Microprocessors; Modems; Permission; Predictive models;
Conference_Titel :
Design Automation Conference, 2000. Proceedings 2000
Print_ISBN :
1-58113-187-9
DOI :
10.1109/DAC.2000.855288
