DocumentCode
2215112
Title
Formal verification of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction
Author
Velev, Miroslav N. ; Bryant, Randal E.
Author_Institution
Carnegie Mellon University
fYear
2000
fDate
2000
Firstpage
112
Lastpage
117
Keywords
Computer aided instruction; Computer science; Delay; Design automation; Formal verification; Logic; Microprocessors; Modems; Permission; Predictive models;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2000. Proceedings 2000
Print_ISBN
1-58113-187-9
Type
conf
DOI
10.1109/DAC.2000.855288
Filename
855288
Link To Document