Title :
A new scalable VLSI architecture for Reed-Solomon decoders
Author :
Wilhelm, Wowgang ; Kaufmann, André ; Noll, Tobias G.
Author_Institution :
Tech. Hochschule Aachen, Germany
Abstract :
A scalable VLSI architecture for Reed-Solomon decoding suited for data rates from 10 Mbit/s to 1.2 Gbit/s in a 0.5 μm-CMOS technology is presented. New regular, time-shared architectures have been derived for solving the key equation and performing finite field divisions. A small silicon area in comparison with state-of-the-art decoder implementations demonstrates the efficiency of the proposed architecture
Keywords :
CMOS digital integrated circuits; Reed-Solomon codes; VLSI; decoding; digital signal processing chips; 0.5 micron; 10 Mbit/s to 1.2 Gbit/s; CMOS technology; Reed Solomon decoders; finite field divisions; scalable VLSI architecture; state-of-the-art decoder implementations; time-shared architectures; CMOS technology; Computer architecture; Decoding; Equations; Error correction codes; Galois fields; Reed-Solomon codes; Space technology; Time sharing computer systems; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-4292-5
DOI :
10.1109/CICC.1998.694898
