Optimization of a bipolar double polysilicon technology using partial factorial arrays and response surface methods

The optimization of critical DC and AC parameters of a double polysilicon bipolar technology for ECL RAM operation is described. In particular, partial factorial arrays and response surface methods are used to optimize simultaneously the current gain and other critical parameters such as cutoff frequency, intrinsic base resistance, emitter-base capacitance, and collector-to-emitter breakdown voltage. The process used is the AMD self-aligned process (ASAP), a self-aligned, trench-isolated, bipolar technology. The use of the optimization method substantially increases the amount of information obtained from a development run, reducing development time and cost