VLSI implementation of hierarchical motion estimator for MPEG2 MP@HL

Author

Onoye, Takao ; Fujita, Gen ; Shirakawa, Isao ; Matsumura, Kenji ; Ariyoshi, Hiromu ; Tsukiyama, Shuji

Author_Institution

Dept. of Inf. Syst. Eng., Osaka Univ., Japan

fYear

1996

fDate

5-8 May 1996

Firstpage

351

Lastpage

354

Abstract

A VLSI motion estimator dedicated to MPEG2 MP@HL has been developed. Adopting a two-level hierarchical searching algorithm in detecting motion vectors, the computational labor can be reduced by 1/70 in comparison with the conventional algorithm. The proposed motion estimator is integrated in a 0.6 μm triple-metal CMOS chip which contains 1,200 K transistors on a 12.2×12.7 mm² die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP@HL

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; image coding; motion estimation; real-time systems; systolic arrays; 0.6 micron; 133 MHz; MPEG2 MP@HL; VLSI implementation; hierarchical motion estimator; input clock rate; motion vectors; real time motion estimation; triple-metal CMOS chip; two-level hierarchical searching algorithm; Application specific integrated circuits; Clocks; Clustering algorithms; Encoding; Information systems; Motion detection; Motion estimation; Navigation; TV broadcasting; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Conference_Location

San Diego, CA

Print_ISBN

0-7803-3117-6

Type

conf

DOI

10.1109/CICC.1996.510573

Filename

510573