A cascadable 200 GOPS motion estimation chip for HDTV applications

Author

Berns, Jan Peter ; Noll, Tobias G.

Author_Institution

Tech. Hochschule Aachen, Germany

fYear

1996

fDate

5-8 May 1996

Firstpage

355

Lastpage

358

Abstract

A flexible block matching motion estimation chip is described with variable sized blocks between 8×8 and 32×32 pixels. Each chip performs block matching with a search area of ±15 vertically and horizontally for a block size of 32×32. For larger search areas devices can be cascaded. Besides full search, fast algorithms can be emulated. Sub-pel precision motion vectors can be calculated using a smaller search area or cascading devices. The chip will have a computational power of more than 200 GOPS and a die size of 170 mm² in an 0.5-μm CMOS technology

Keywords

CMOS digital integrated circuits; cascade networks; digital signal processing chips; high definition television; image matching; image processing equipment; motion estimation; telecommunication computing; 0.5 micron; CMOS technology; HDTV applications; block matching; cascadable motion estimation chip; fast algorithm emulation; sub-pel precision motion vectors; variable sized blocks; Application software; CMOS technology; Design for disassembly; HDTV; Image coding; Image sequences; Interpolation; Motion detection; Motion estimation; Shape;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Conference_Location

San Diego, CA

Print_ISBN

0-7803-3117-6

Type

conf

DOI

10.1109/CICC.1996.510574

Filename

510574