Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration

Field programmable logic is increasingly used to provide the high performance and flexible acceleration needed for network processing functions at multiple gigabit/second rates. Almost all such functions feature the use of clocks and timers in control and/or data roles, and these are typically implemented in an ad hoc manner. This paper introduces a set of three configurable timing modules that are based on abstractions of the prevalent timing paradigms observed in network protocols. The modules fit within the experimental ShapeUp methodology for modular FPGA-based system design, and so can be easily integrated with other modules that are tailored for specific networking functions. The use and benefits of the new modular approach are demonstrated by an example of a flexible FPGA reference design that has been made available for real-life use by telecommunication equipment providers.