Control and synchronization scheme for parallel image processing RAM with 128 processor elements and 16-Mb DRAM

Author

Yabe, Yoshikazu ; Kimura, Tohru ; Aimoto, Yoshiharu ; Heiuchi, Hideki ; Nakazawa, Yoshihiro ; Koga, Takuya ; Fujita, Yoshihiro ; Hamada, Masayuki ; Tanigawa, Tarkaho ; Nobusawa, Hajime ; Koyama, Kuniaki

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1996

fDate

5-8 May 1996

Firstpage

363

Lastpage

366

Abstract

A newly developed parallel image processing RAM (PIP-RAM) integrates 128 processor elements and a 16-Mb DRAM on a single chip. The paper presents three novel circuit design techniques: a data path control and synchronization scheme between processors and memory; a refresh scheme which enables refresh operations in parallel with arithmetic-logical operations; and a special block redundancy scheme

Keywords

CMOS memory circuits; DRAM chips; digital signal processing chips; image processing; image processing equipment; parallel architectures; redundancy; synchronisation; 16 Mbit; CMOS IC; DRAM; block redundancy scheme; control scheme; data path control; design techniques; parallel image processing RAM; processor elements; refresh operations; refresh scheme; synchronization scheme; Delay; Image processing; National electric code; Parallel processing; Power dissipation; Random access memory; Read-write memory; Signal processing; Size control; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Conference_Location

San Diego, CA

Print_ISBN

0-7803-3117-6

Type

conf

DOI

10.1109/CICC.1996.510576

Filename

510576