DocumentCode
2215417
Title
A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance
Author
Mehrotra, Vikas ; Sam, Shiou Lin ; Boning, Duane ; Chandrakasan, Anantha ; Vallishayee, Rakesh ; Nassif, Sani
Author_Institution
Massachusetts Institute of Technology
fYear
2000
fDate
2000
Firstpage
172
Lastpage
175
Keywords
Aluminum; Capacitance; Circuit analysis; Circuit optimization; Clocks; Copper; Delay effects; Design automation; Integrated circuit interconnections; Permission;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2000. Proceedings 2000
Print_ISBN
1-58113-187-9
Type
conf
DOI
10.1109/DAC.2000.855298
Filename
855298
Link To Document