High-radix logarithm with selection by rounding

Author

Piñeiro, J.A. ; Ercegovac, M.D. ; Bruguera, J.D.

Author_Institution

Dept. of Electron. & Comput. Eng., Santiago de Compostela Univ., Spain

fYear

2002

fDate

2002

Firstpage

101

Lastpage

110

Abstract

A high-radix digit-recurrence algorithm or the computation of the logarithm is presented in this paper. Selection by rounding is used in iterations j≥2, and selection by table in the first iteration is combined with a restricted digit-set for the second one, in order to guarantee the convergence of the algorithm. A sequential architecture is proposed. and the execution time and hardware requirements of this architecture are estimated, for a target precision of n=32 bits and a radix r=256. These estimates are obtained according to a rough model for the delay and area cost of the main logic blocks employed, and show the achievement of a speed-up by over 4 times with regard to a conventional radix-2 implementation with redundant arithmetic.

Keywords

convergence of numerical methods; delay estimation; digital arithmetic; iterative methods; logic design; sequential circuits; algorithm convergence; delay model; execution time; hardware requirements; high-radix digit-recurrence algorithm; high-radix logarithm; iterations; logarithm computation; logic block area cost model; radix-2 implementation; redundant arithmetic; restricted digit-set; rounding based selection; sequential architecture; table based selection; target precision; Application software; Arithmetic; Computer architecture; Computer science; Convergence; Costs; Delay estimation; Hardware; Logic; Polynomials;

fLanguage

English

Publisher

ieee

Conference_Titel

Application-Specific Systems, Architectures and Processors, 2002. Proceedings. The IEEE International Conference on

ISSN

2160-0511

Print_ISBN

0-7695-1712-9

Type

conf

DOI

10.1109/ASAP.2002.1030708

Filename

1030708