DocumentCode :
2215589
Title :
A Compact Transactional Memory Multiprocessor System on FPGA
Author :
Pusceddu, Matteo ; Ceccolini, Simone ; Palermo, Gianluca ; Sciuto, Donatella ; Tumeo, Antonino
Author_Institution :
Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy
fYear :
2010
fDate :
Aug. 31 2010-Sept. 2 2010
Firstpage :
578
Lastpage :
581
Abstract :
In this paper we present a rapid prototyping platform on a single Field Programmable Gate Array (FPGA) with support for software transactional memory. The system is composed only by off-the-shelf cores and is useful for porting and early validation of programs to the transactional memory programming model. We discuss the implementation of the software layer of this platform, propose an analysis of the system and compare it to a hardware lock based multiprocessor architecture, showing the trade-offs in terms of performance and programming complexity.
Keywords :
field programmable gate arrays; microprocessor chips; FPGA; compact transactional memory multiprocessor system; field programmable gate array; hardware lock based multiprocessor architecture; off-the-shelf cores; performance complexity; programming complexity; software transactional memory; FPGA; Multiprocessor; Prototyping; Transactional Memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2010 International Conference on
Conference_Location :
Milano
ISSN :
1946-1488
Print_ISBN :
978-1-4244-7842-2
Type :
conf
DOI :
10.1109/FPL.2010.113
Filename :
5694314
Link To Document :
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