• DocumentCode
    2215616
  • Title

    A 10-bit, 100 MS/s CMOS A/D converter

  • Author

    Kim, K.Y. ; Kusayanagi, N. ; Abidi, A.A.

  • fYear
    1996
  • fDate
    5-8 May 1996
  • Firstpage
    419
  • Lastpage
    422
  • Abstract
    This work addresses some of the known problems inherent in time-interleaved, or parallel, ADCs with a new architecture. A prototype of this architecture demonstrates, for the first time, 10-bit operation at 100 MS/s in a 1 μm CMOS technology
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; parallel architectures; 1 micron; 10 bit; ADC architecture; CMOS A/D converter; parallel ADC; time-interleaved ADC; Bandwidth; CMOS technology; Circuits; Clocks; Dynamic range; Pipelines; Power dissipation; Signal processing; Throughput; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-3117-6
  • Type

    conf

  • DOI
    10.1109/CICC.1996.510588
  • Filename
    510588
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2215616