A mathematical model of trace cache

Wide-issue superscalar processors have capabilities to execute several basic blocks in a cycle. A regular instruction cache fetch mechanism is not capable of supporting this high fetch throughput requirement. Several improvements of the fetch mechanism are currently in use. One of the most successful of these improvements is the addition of an instruction memory structure known as a trace cache. In this paper an analytical model of instruction fetch performance of a trace cache microarchitecture is presented. Parameters, which affect trace cache instruction fetch performance, are explored and several analytical expressions are presented. The presented model can be used to understand performance tradeoffs in trace cache design. Results from the validation of the model are presented. The instruction fetch rates predicted by the model differ by seven percent from the simulated fetch rates for SPEC2000 benchmark programs. The model is implemented in a computer program named Tulip. To show how different parameters influence performance, results from Tulip are also presented.