Implementation of a 32-bit RISC processor for the data-intensive architecture processing-in-memory chip

The Data-Intensive Architecture(DIVA) system employs Processing-In-Memory(PIM) chips as smart-memory coprocessors to a micorprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system to target several classes of bandwidth- limited applications, including multimedia applications and pointer-based and sparse-matrix computations. The DIVA project is building a prototype workstation-class system using PIM chips in place of standard DRAMs to demonstrate these concepts. We have recently completed initial testing of the rst version of the prototype PIM device. A key component of this architecture is the scalar processor that coordinates all activ-ity within a PIM node. Since such a component is present in each PIM node,we exploit parallelism to achieve significant speedups rather than relying on costly, high-performance processor design. The resulting scalar processor is then an in-order 32-bit RISC microcontroller that is extremely area-efficient. This paper details the design and implementation of this scalar processor in TSMC 0.18cm technology. In conjunction with other publications, this paper demonstrates that impressive gains can be achieved with very little "smart" logic added to memory devices.