Title :
PAPA - packed arithmetic on a prefix adder for multimedia applications
Author_Institution :
Sch. of Eng., Cardiff Univ., UK
Abstract :
This paper introduces PAPA: packed arithmetic on a prefix adder, a new approach to parallel prefix adder design that supports a wide variety of packed arithmetic computations, including packed add and subtract with saturation, packed rounded average, and packed absolute difference. The approach consists of altering the prefix adder cell logic equations to take advantage of a previously unused "don\´t care" state. The principle of logical effort is employed to assess the delay of the new adder architecture by establishing the extra effort needed to select and drive the appropriate carry signal to the requisite sum sub-word. This adder will find applications in video processors and other multimedia-orientated processor chips that implement packed arithmetic operations.
Keywords :
adders; digital arithmetic; digital signal processing chips; integrated circuit design; integrated circuit modelling; logic design; multimedia systems; PAPA; adder architecture delays; driven carry signal selection; logical effort analysis; multimedia applications; multimedia-orientated processor chips; packed absolute difference; packed add/subtract with saturation; packed arithmetic computations; packed arithmetic on prefix adder; packed arithmetic operations; packed rounded average; parallel prefix adder design; prefix adder cell logic equations; sum sub-word; unused don´t care state; video processors; Acceleration; Adders; Arithmetic; Computer architecture; Concurrent computing; Design engineering; Equations; Logic; Signal generators; Signal processing algorithms;
Conference_Titel :
Application-Specific Systems, Architectures and Processors, 2002. Proceedings. The IEEE International Conference on
Print_ISBN :
0-7695-1712-9
DOI :
10.1109/ASAP.2002.1030719