DocumentCode
2215840
Title
Reviewing 4-to-2 adders for multi-operand addition
Author
Kornerup, Peter
Author_Institution
Dept. of Math. & Comput. Sci., Southern Danish Univ., Odense, Denmark
fYear
2002
fDate
2002
Firstpage
218
Lastpage
229
Abstract
Recently there has been quite a number of papers discussing the use of redundant 4-to-2 adders for the accumulation of partial products in multipliers, claiming one type to be superior to other types. This paper analyses the use of various 3- and 4-element redundant digit sets for radix 2, and compares their adder implementations using various encodings of the digits and carries. It is shown that theoretically they are equivalent, and differences in their implementations need only be very marginal. Another recent proposal for the use of the digit-set {0, 1, 2, 3}, with a special 3-bit encoding of digits, is analyzed and some optimizations are shown, including the possibility of using a 2-bit encoding, simplifying the wiring of a multiplier tree. All these proposed designs are shown to be equivalent to a standard 4-to-2, carry-save adder except possibly for a few signal inversions.
Keywords
VLSI; adders; circuit optimisation; multiplying circuits; redundancy; 4-to-2 adders; VLSI; multi-operand addition; multiplier tree; optimizations; partial products; redundant digit sets; signal inversions; Binary trees; Computer science; Encoding; Mathematics; Proposals; SPICE; Signal design; Tree data structures; Very large scale integration; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Application-Specific Systems, Architectures and Processors, 2002. Proceedings. The IEEE International Conference on
ISSN
2160-0511
Print_ISBN
0-7695-1712-9
Type
conf
DOI
10.1109/ASAP.2002.1030721
Filename
1030721
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