Title :
IDDQ testing in low power supply CMOS circuits
Author :
Tong, Carol Q. ; Wen, Mindy ; Su, Shyang Tai
Author_Institution :
Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
Abstract :
The IDDQ current testing for low power circuits is investigated. Two examples of low power circuits are considered. One involves strictly a decrease in supply voltage, the other reduces supply voltage simultaneously with a scaling down of transistor parameters. Based on the theoretical and simulation results, the gap between faulty IDDQ and fault-free IDDQ can be seen to decrease in low power supply circuits. For IDDQ testing to be effective, the gap should be discriminative. A method of partitioning is provided to solve this problem
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit testing; leakage currents; CMOS circuits; IDDQ testing; low power circuits; partitioning method; supply voltage reduction; Circuit faults; Circuit testing; Electrical fault detection; Energy consumption; Fault detection; Leakage current; Logic testing; Monitoring; Packaging; Power supplies;
Conference_Titel :
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-3117-6
DOI :
10.1109/CICC.1996.510598
