Title :
Fast post-placement rewiring using easily detectable functional symmetries
Author :
Chang, Chih-Wei Jim ; Cheng, Chung-Kuan ; Suaris, Peter ; Marek-Sadowska, Malgorzata
Author_Institution :
University of California
Keywords :
Circuit synthesis; Connectors; Convergence; Design engineering; Integrated circuit interconnections; Logic; Network synthesis; Permission; Timing; Wires;
Conference_Titel :
Design Automation Conference, 2000. Proceedings 2000
Print_ISBN :
1-58113-187-9
DOI :
10.1109/DAC.2000.855320
